As device feature sizes and associated design rules continue to be driven smaller, transistors having a general horizontal channel structure are increasingly more difficult to manufacture. There appears to be some limitations to the ability to scale down horizontal channel structure transistors. One potentially serious limitation is a short channel effect and a drain induced barrier lower (DIBL) effect, which can occur more often as the channel length is shortened. When the channel length is reduced to 50 nm or less in some conventional transistors, the degree of dispersion of the device characteristics increases due to variability in the parameters of the fabrication process. Moreover, if the channel length is reduced to 30 nm or less, it is known to be more difficult for a transistor to exhibit desired operational characteristics because of strong short channel effects and DIBL effects.
In conventional transistors, a gate electrode may be formed over only the horizontal channel so that an electric field is applied asymmetrically to upper and lower portions of the channel. As a result, the gate electrode may not effectively control the transistor between ON/OFF states, and short channel effects due to the reduction of the channel length can become a serious problem.
A double gate transistor is a type of device that has been researched in an attempt to overcome problems associated with transistors having horizontal channel structures. The double gate transistor can have a structure in which the channel is formed to be 30 nm or less thick, and a gate encompasses the channel or is disposed on both sides of the channel. Because the gate electrode is formed on both sides of the thin channel in the double gate transistor, every region of the channel is influenced by the gate electrode. Therefore, because charge flow can be inhibited between a source and a drain when the transistor is turned off, it may be possible to reduce power consumption. Further, it may be possible to effectively control the transistor between ON/OFF states. In the double gate MOS transistor, the width of a silicon layer in which the channel is formed is small, so it is possible to increase the controllability of the gate with respect to the channel. Because the silicon layer can have a width that is in a range of nanometers to tens of nanometers, the double gate transistor is also called a fin field effect transistor (FinFET) due to its shape.
A floating trap type nonvolatile memory device with a FinFET structure will now be explained. Referring to FIG. 17, a plurality of fins 101 are arranged in the shape of lines which extend away from a semiconductor substrate 100, and a device isolation layer 102 is disposed between the fins 101. A plurality of word lines 110, which are parallel with one another, cross over the fins 101. Between the word lines 110 and the fins 101, there are interposed a tunnel insulating layer 104, a charge storage layer 106, and a blocking insulating layer 108 which are stacked in sequence.
When programming a first cell transistor TR1, a program voltage is applied to a corresponding word line 110 and a predetermined voltage, e.g., 0 V, is applied to a channel region of the first cell transistor TR1 so that charges are trapped in the charge storage layer 106 of the first cell transistor TR1 in response to a large voltage difference. At this time, a channel region of an adjacent second cell transistor TR2 is maintained to be a floating voltage higher than 0 V, for example. However, if the device isolation layer 102 is thin, a channel is also formed under the device isolation layer 102 and a leakage current flows in the direction of the illustrated arrow of FIG. 17. Resultingly, there may occur a program disturbance by which the second cell transistor TR2 is undesirably programmed.
In an attempt to avoid the undesirable programming of an adjacent non-selected cell transistor, the device isolation layer 102 may be formed thicker than a predetermined thickness. However, the thickness of the device isolation layer 102 is restricted by the height of the fin 101. Another approach may be to isolate the fin from adjacent fins by forming the fin 101 on a silicon-on-insulator (SOI) substrate. However, SOI substrate processes can be very expensive and a back bias may not be applied thereto.